`timescale 1ns/10ps
module nor_gate(A,B,Y);
input A,B;
output Y;
assign Y=~(A|B);
endmodule 


module nor_gate_tb;
reg A,B;
wire Y;
nor_gate nor_gate(.A(A),.B(B),.Y(Y));
initial 
      begin
          A<=0;B<=0;
          #10
          A<=1;B<=0;
          #10
          A<=0;B<=1;
          #10
          A<=1;B<=1;
          #10
          $stop;
end
endmodule
